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Keynote Speakers

We are very pleased to announce details of our Keynote Speakers:

Wednesday 14th May 2014

Dr. John Rowlands, Typhoon Engineering Integration Manager, BAE SYSTEMS

The Changing Shape of Products and Their Safety Cases

Dr. John Rowlands is the BAE SYSTEMS Technical Integration Manager responsible for identifying technologies and capabilities that will be integrated into Eurofighter Typhoon in 2020 and beyond.

Abstract: This presentation will describe some of the ways in which the company’s products have evolved and the impact that has on the way we think about safety. Those challenges result from the need to support multiple customers with diverse needs, to extract the maximum performance from the product and to update the product rapidly in response to new requirements. This will hopefully stimulate some thoughts regarding the way in which these challenges can be approached and the synergy with other products and industries.

Thursday 15th May 2014

Prof Ian Phillips, Principal Staff Engineer, ARM Ltd


Where did all the errors go?

Abstract: As the physical process geometry got smaller on an 18mth tick, the number of transistors on a chip grew inexorably to the low billions we encounter today. Can we honestly say we are 99.9999999% sure our designs are correct? And the transistors got smaller not only were there more of them on a chip, but each becomes more susceptible to high energy particles. So how often do we have to wait before a stray particle causes a bit to flip, and how many bit-flips before a functional error occurs? And how about software, we know that even the best quality code has more than one error per thousand lines of source, so how many of them translates to unexpected state and timing errors? And what is the consequence of a failure?

... Then there’s reliability; hot electrons, electromigration and spikes; making transistors wear out in use. And then there’s intrinsic variability caused as the statistical nature of matter becomes obvious as device geometries approach atomic dimensions. This produces predictable Gaussian spreads of device parametrics, including the odd ones that have no transistor action at all! And finaly there is good old fashioned noise, arbitrarily producing supply glitches as multiple outputs are called to swing in unison; effecting the timing of countless gates as they experience reduced supply voltages for the odd uS.

Clearly in the 21C, design-it-right has its limitations, and so does keep-it-right ... when will this perfect storm strike? In fact, pundits with calculators have been predicting the ‘end of the world’ since about 130nm. A point beyond which the pact between silicon and mathematics would become inadequate to support our design methodology based on a “100% correct” model. So here we are today at 20/24nm, with an abundance of evidence that disaster has not struck. With 14nm on the drawing boards; commercially, it is business as usual!

So where did all the errors go?